Specifications

Index
Index-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
SCI 12-6
signals 2-32
SSMC 13-9
SSP 14-4
Watchdog 19-3
Core
DMA APB 3-3
Current requirements B-4
D
DMA
APB base address 3-30
support 1-13
DMA APB 3-3
DMAC 1-6
features 8-2
interrupt source 8-5
master interfaces 8-5
pad signals 8-7
peripheral request lines 8-5
DOZE mode 2-7, 2-10
Dynamic memory 10-4
E
Electrical characteristics B-3
Embedded Trace Macrocell 1-6
Endianness 3-14
ETM9 1-6
F
FIFO 16-2
FIQ 17-2
Frame synchronization 5-23
G
GPIO
features 9-2
pad signals 9-5
H
Hardware cursor
cursor clipping 5-9
image format 5-11
pixel encoding 5-16
support 5-3, 5-7
supported cursor sizes 5-8
Windows CE software format 5-14
32x32 pixels 5-12
64x64 pixels 5-13
I
IEEE 754 standard compliance 18-2,
18-6
Default NaN mode 18-6
Flush-to-Zero mode 18-6
Full-compliance mode 18-6
RunFast mode 18-2, 18-6
subnormal inputs 18-6
VFP9 RunFast mode 18-8
Interrupts
cursor 5-24
RTCINTR 11-4
SCI 12-5
system controller mode 2-3
Timer 15-2
VIC 17-2
wait for interrupt 2-3
IrDA SIR ENDEC 16-2, 16-3
IRQ 17-2
J
JEDEC SDRAM devices 10-4
M
MBX
block diagram 7-2
operation 1-5
Memory
controller selection 3-17
map 1-11
MMU address translation 7-8
MPMC 10-1
SSMC 13-1
supported 13-4
timing C-4
Modem
control functions 16-3
MOVE 6-2
coprocessor 1-4
structure 6-2
MPMC 1-5
block diagram 10-6
features 10-2
pad signals 10-8
port allocation 1-10
ROM devices 10-5
N
Nonvectored interrupt 17-3, 17-6
O
Overview 1-7
P
Pad signals
AHB monitor 4-42
CLCDC 5-31
DMAC 8-7
function A-1
GPIO 9-5
MPMC 10-8
SCI 12-6
SSMC 13-9, A-1
SSP 14-6
system controller 2-30
UART 16-8
VIC 17-11
Page mode
ROM devices 10-5
PLL
control transition state 2-11