Specifications

Introduction

For more information on the timers, see the ARM Dual-Timer Module

(SP804) Technical Reference Manual and Chapter 15 Dual

Timer/Counters.

Watchdog module

This is used to trigger a system reset in the event of software failure.

The release version used is SP805 WDOG r1p0-02ltd0.

For more information on the Watchdog monitor, see the ARM PrimeCell

Watchdog Controller (SP805) Technical Reference Manual and

Chapter 19 Watchdog Timer.

Universal Asynchronous Receiver-Transmitter (UART)

There are three UARTs in the ARM926EJ-S Development Chip. The

UARTs perform serial-to-parallel conversion on data received from a

peripheral device

The release version used is PL011 UART 1v3.

For more information on the UARTs, see the ARM PrimeCell UART

(PL011) Technical Reference Manual and Chapter 16 UART Controller.

Synchronous Serial Port (SSP)

The PrimeCell SSP is a master or slave interface that enables

synchronous serial communication with slave or master peripherals

having one of the following:

• a Motorola SPI-compatible interface

• a Texas Instruments synchronous serial interface

• a National Semiconductor Microwire interface.

The release version used is PL022 SSP REL1v2.

For more information on the SSP, see the ARM PrimeCell Synchronous

Serial Port Controller (PL022) Technical Reference Manual and

Chapter 14 Synchronous Serial Port (SSP).

Color Liquid Crystal Display Controller (CLCDC)

The CLCDC performs translation of pixel-coded data into the required

formats and timings to drive a variety of single/dual mono and color

LCDs. Support is provided for passive Super Twisted Nematic (STN) and

active Thin Film Transistor (TFT) LCD display types.

The release version used is a modified PL110 CLCDC r0p0-00alp0 with

the hardware cursor from the PL111.