Specifications

Timing Specification
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. C-5
C.4 Peripheral timing
Table C-3 shows the peripheral and controller timing. For more detail on timing and
example waveforms, see the relevant Technical Reference Manual for the module.
Table C-3 Peripherals and controller timing
Peripheral signals Clock tov toh tis tih
CLCDC outputs (CLD[23:0], CLPOWER, CLLP, CLCP,
CLFP, CLAC, and CLLE)
The maximum frequency of CLCDCLK is 100MHz for a
tcyc
of 10ns.
CLCDCLK 12.5ns -2.5ns - -
DMAC outputs (DMACCLR[5:0] and DMACTC[5:0]) HCLK 3ns 0ns - -
DMAC inputs (DMACLBREQ[5:0], DMACLSREQ[5:0],
DMACBREQ[5:0] and DMACSREQ[5:0] )
HCLK - - 4ns 0ns
SCI outputs (nSCICLKOUTEN, SCICLKOUT,
nSCIDATAOUTEN, nSCICLKEN, and nSCIDATAEN)
SCIREFCLK 14ns -1ns - -
SCI inputs (SCICLKIN, SCIDATAIN, and SCIDETECT)
The maximum frequency of SCIREFCLK is 100MHz for a
tcyc of 10ns.
SCIREFCLK - - 12ns -14ns
SSP outputs (SSPFRMOUT, SSPCLKOUT, SSPTXD,
nSSPCTLOE, and nSSPOE)
SSPCLK 4ns -2ns - -
SSP inputs (SSPRXD, SSPFRMIN, and SSPCLKIN)
The maximum frequency of SSPCLK is 100MHz for a tcyc of
10ns.
SSPCLK - - 12ns -14ns
VIC inputs (VICINTSOURCE[31:21] and PWRFAIL) HCLK - - 4ns 0ns