Specifications
Mechanical and Electrical Specifications
B-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
B.2.2 Power estimation
Table B-3 shows the maximum power requirements.
B.2.3 Power sequencing
There is an internal parasitic diode path from core voltage to I/O voltage. If the lower
core voltage is powered up earlier than the higher I/O voltage, current flow through the
parasitic diode can cause latchup.
To prevent latchup, ensure that the higher I/O voltage is powered on before the core
voltage.
Caution
If you cannot ensure that the I/O voltage is always higher than the core voltage, use a
low-voltage drop Schottcky diode between the two supplies (anode to VDDC and
cathode to VDDIO).
Table B-3 Power estimate
Description Power
Total Logic, RAM and Clock Tree Power 1 W
Total I/O Power 3.5W
Total 4.5 W