Specifications

Signals on Pads

MPMC MPMCDATA[31] Data bus B 8 AE7

MPMC MPMCDQM[0] Data mask & byte lane select O 8 V2

MPMC MPMCDQM[1] Data mask & byte lane select O 8 W7

MPMC MPMCDQM[2] Data mask & byte lane select O 8 V4

MPMC MPMCDQM[3] Data mask & byte lane select O 8 Y5

MPMC MPMCFBCLK Clock feedback I - U4

MPMC MPMCRPVHHOUT Select Vh level for nRP O 4 AF5

MPMC nMPMCCAS Column address strobe O 12 W2

MPMC nMPMCDYCS[0] Synch memory chip enable O 8 Y6

MPMC nMPMCDYCS[1] Synch memory chip enable O 8 Y1

MPMC nMPMCDYCS[2] Synch memory chip enable O 8 Y7

MPMC nMPMCDYCS[3] Synch memory chip enable O 8 Y2

MPMC nMPMCRAS Row address strobe O 12 W1

MPMC nMPMCRPOUT SyncFlash reset power down O 4 AJ3

MPMC nMPMCWE Write enable O 12 W3

Power TAVDD PLL digital power PIO - C4

Power TAVSS PLL digital ground PIO - F7

Power TVDD1P PLL analog power PIO - G8

Power TVSS1P PLL analog ground PIO - F6

Power VDDC[0] Core Power PC - F2

Power VDDC[1] Core Power PC - J4

Power VDDC[2] Core Power PC - N2

Power VDDC[3] Core Power PC - V3

Power VDDC[4] Core Power PC - AA1

Power VDDC[5] Core Power PC - AE1

Table A-1 Pad signals (continued)

Function Signal Description Type Drive BGA