Specifications

Introduction

1.2 Functional description

The ARM926EJ-S Development Chip comprises the following functional blocks:

ARM926EJ-S

This is a cached ARM CPU including Instruction and Data caches,

Memory Management Unit (MMU), and Tightly Coupled Memory

(TCM). It supports the Jazelle

extensions for Java acceleration.

The ARM926EJ-S processor used with the ARM926EJ-S Development

Chip is configured with 32KB instruction and data caches and 32KB

TCMs.

The release version used is ARM926EJ-S r0p3-00rel0. The PrimeXsys

Wireless Platform version is r2p0.

For more information on the ARM926EJ-S, see the ARM926EJ-S

Technical Reference Manual.

MOVE coprocessor

The MOVE coprocessor is a video encoding acceleration coprocessor

designed to accelerate Motion Estimation (ME) algorithms within

block-based video encoding schemes such as MPEG4 and H.263. This is

done by providing support for the execution of Sum of Absolute

Differences (SAD) calculations, which account for most of the

processing activity within an ME algorithm. These algorithms require

many comparisons between 8x8 pixel blocks to made between a current

frame and a reference frame.

The release version used is MOVE r3p0-00bet0.

For more information on the MOVE coprocessor, see the ARM MOVE

Coprocessor Technical Reference Manual and Chapter 6 MOVE

Coprocessor.

VFP9 coprocessor

The VFP9-S coprocessor is an implementation of the Vector

Floating-Point architecture version 2 (VFPv2) and provides

floating-point computation that is fully compliant with the ANSI/IEEE

Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic. The

VFP9-S coprocessor supports all addressing modes described in section

C5 of the ARM Architecture Reference Manual.

The release version used is VFP9-S r1p1.

For more information on the VFP9 coprocessor, see the ARM VFP9-S

Coprocessor Technical Reference Manual and Chapter 18 ARM Vector

Floating Point Coprocessor (VFP9).