Specifications

Watchdog Timer

19.1 About the Watchdog module (SP805)

The Watchdog module is an Advanced Microcontroller Bus Architecture (AMBA)

compliant System-on-Chip (SoC) peripheral developed, tested, and licensed by ARM

Limited.

The release state of the Watchdog Module used in the ARM926EJ-S Development Chip

is SP805-r1p0. The base address for the Watchdog control registers is

0x101E1000

. For

more information on the controller, see the ARM PrimeCell Watchdog Controller

(SP805) Technical Reference Manual.

The Watchdog module is an AMBA slave module and connects to the core APB. The

Watchdog module consists of a 32-bit down counter with a programmable timeout

interval that has the capability to generate an interrupt and a reset signal on timing out.

It is intended to be used to apply a reset to a system in the event of a software failure.

19.1.1 Features

The features of the Watchdog module are:

• Compliance to the AMBA Specification (Rev 2.0) for easy integration into an SoC

implementation.

• 32-bit down counter with a programmable timeout interval.

• Separate Watchdog clock with clock enable for flexible control of the timeout

interval.

• Interrupt output generation on timeout.

• Reset signal generation on timeout if the interrupt from the previous timeout

remains unserviced by software.

• Lock register to protect registers from being altered by runaway software.

• Identification registers that uniquely identify the Watchdog module. These can be

used by software to automatically configure itself.