Specifications

ARM Vector Floating Point Coprocessor (VFP9)

• A float-to-integer conversion that has the potential to create an integer that cannot

be represented in the destination integer format when Invalid Operation

exceptions are enabled.

The support code:

• determines the nature of the exception

• determines if processing is required to perform the computation

• calls a user trap handler

• transfers control to the user trap handler if the enable bit for the detected

exception is set

• writes the result to the destination register, updates the FPSCR register, and

returns to the user code if the exception enable bit is not set.

18.4.2 Flush-to-Zero mode

Setting the FZ bit, FPSCR[24], enables Flush-to-Zero mode and increases performance

on very small inputs and results. In Flush-to-Zero mode, the VFP9-S coprocessor treats

all subnormal input operands of arithmetic CDP operations as positive zeros in the

operation. Exceptions that result from a zero operand are signaled appropriately. FABS,

FCMP, and FNEG are not considered arithmetic CDP operations, and are not affected

by Flush-to-Zero mode. A result that is tiny, as described in the IEEE 754 standard, for

the destination precision is smaller in magnitude than the minimum normal value before

rounding and is replaced with a positive zero. The IDC flag, FPSCR[7], indicates when

an input flush occurs. The UFC flag, FPSCR[3], indicates when a result flush occurs.

18.4.3 Default NaN mode

Setting the DN bit, FPSCR[25] enables Default NaN mode. In Default NaN mode, the

result of any operation that involves an input NaN or generated a NaN result returns the

default NaN. Propagation of the fraction bits is maintained only by FABS, FNEG, and

FCPY operations, all other CDP operations ignore any information in the fraction bits

of an input NaN.