Specifications

ARM Vector Floating Point Coprocessor (VFP9)
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 18-5
Access to the FPEXC, FPINST, and FPINST2 registers is possible only in a privileged
mode, and does not trigger exceptions. Use the
FMRX instruction to store these registers
and the
FMXR instruction to load them. Table 18-1 describes access to these registers.
Table 18-1 Access to control registers
Register
FMXR/FMRX <reg>
field encoding
Exception processing
trigger? Legal modes
FPSID 0000 No Any
FPSCR 0001 No Any
FPEXC 1000 No Privileged
FPINST 1001 No Privileged
FPINST2 1010 No Privileged