Specifications

ARM Vector Floating Point Coprocessor (VFP9)

18.3 VFP9-S system control and status registers

The VFP9-S coprocessor provides sufficient information for processing all exception

conditions encountered by the hardware. In an exceptional situation, the hardware

provides:

• the exceptional instruction

• the instruction that was issued to the VFP9-S coprocessor before the exception

was detected

• exception status information

— type of exception

— number of remaining short vector iterations after an exceptional iteration.

Five VFP9-S registers support exceptional conditions:

• Floating-point System ID Register (FPSID)

• Floating-point Status and Control Register (FPSID)

• Floating-point Exception Register (FPEXC).

• Floating-point Instruction Register (FPINST)

• Floating-point Instruction Register 2 (FPINST2)

These registers are designed to be used with the support code software available from

ARM Limited. As a result, this document does not fully specify exception handling in

all cases.

In addition, the source data registers for an exceptional instruction are available to the

support code. However, some or all of the other data registers in the ARM9E processor

and the VFP9-S coprocessor might be modified and not in the state they were in at the

time the exceptional instruction was issued.