Specifications

Vectored Interrupt Controller (VIC)
17-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
17.2.2 Nonvectored FIQ interrupt logic
The nonvectored FIQ interrupt logic generates the FIQ interrupt signal by combining
the FIQ interrupt requests in the interrupt controller and any requests from
daisy-chained interrupt controllers. Figure 17-3 shows a block diagram of the
nonvectored FIQ interrupt logic.
Figure 17-3 Nonvectored FIQ interrupt logic
17.2.3 Nonvectored IRQ interrupt logic
The nonvectored IRQ interrupt logic combines the nonvectored interrupt requests to
generate the nonvectored IRQ interrupt signal. This signal is then sent to the IRQ vector
address and priority logic. Figure 17-4 shows a block diagram of the nonvectored IRQ
interrupt logic.
Figure 17-4 Nonvectored IRQ interrupt logic