Specifications

Vectored Interrupt Controller (VIC)
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 17-5
17.2.1 Interrupt request logic
The interrupt request logic receives the interrupt requests from the peripheral and
combines them with the software interrupt requests. It then masks out the interrupt
requests that are not enabled, and routes the enabled interrupt requests to either IRQ or
FIQ. Figure 17-2 shows a block diagram of the interrupt request logic.
Figure 17-2 Interrupt request logic