Specifications

Vectored Interrupt Controller (VIC)

Only a single FIQ source at a time is generally used in a system, to provide a true

low-latency interrupt. This has the following benefits:

• You can execute the interrupt service routine directly without determining the

source of the interrupt.

• Interrupt latency is reduced. You can use the banked registers available for FIQ

interrupts more efficiently, because a context save is not required.

There are 32 interrupt lines. The VIC uses a bit position for each different interrupt

source. The software can control each request line to generate software interrupts.

There are 16 vectored interrupts. These interrupts can only generate an IRQ interrupt.

The vectored and nonvectored IRQ interrupts provide an address for an Interrupt

Service Routine (ISR). Reading from the vector interrupt address register,

VICVectAddr, provides the address of the ISR, and updates the interrupt priority

hardware that masks out the current and any lower priority interrupt requests. Writing

to the VICVectAddr register, indicates to the interrupt priority hardware that the current

interrupt is serviced, permitting lower priority interrupts to go active.

The FIQ interrupt has the highest priority, followed by interrupt vector 0 to interrupt

vector 15. Nonvectored IRQ interrupts have the lowest priority. A programmed interrupt

request enables you to generate an interrupt under software control. This register is

typically used to downgrade an FIQ interrupt to an IRQ interrupt.

Note

The priority of the FIQ over IRQ is set by the ARM. The VIC can raise both an FIQ and

an IRQ at the same time.

The IRQ and FIQ request logic has an asynchronous path. This permits interrupts to be

asserted when the clock is disabled.