Specifications

Vectored Interrupt Controller (VIC)

17.1 About the ARM PrimeCell Vectored Interrupt Controller (PL190)

The PrimeCell Vectored Interrupt Controller (VIC) is an Advanced Microcontroller Bus

Architecture (AMBA) compliant, System-on-Chip (SoC) peripheral that is developed,

tested, and licensed by ARM.

The release version used is PL190 VIC 1v1. The base address for the VIC control

registers is

0x10140000

. For more information on the controller, see the ARM PrimeCell

Vector Interrupt Controller (PL190) Technical Reference Manual.

The PrimeCell VIC provides an interface to the interrupt system, and improves interrupt

latency in two ways:

• moves the interrupt controller to the AMBA AHB bus

• provides vectored interrupt support for high-priority interrupt sources.

17.1.1 Features of the PrimeCell VIC

The PrimeCell VIC has the following features:

• compliance to the AMBA Specification (Rev 2.0) onwards for easy integration into

System-on-Chip (SoC) implementation

• support for 32 standard interrupts

• support for 16 vectored IRQ interrupts

• hardware interrupt priority

• IRQ and FIQ generation

• AHB mapped for faster interrupt response

• software interrupt generation

• test registers

• raw interrupt status

• interrupt request status

• interrupt masking

• privileged mode support

• vector interrupt controller daisy chaining support.

The PrimeCell Vectored Interrupt Controller (VIC) provides a software interface to the

interrupt system. In an ARM system, two levels of interrupt are available:

• Fast Interrupt Request (FIQ) for fast, low latency interrupt handling

• Interrupt Request (IRQ) for more general interrupts.