Specifications

UART Controller
16-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
Programmable parameters
The following key parameters are programmable:
• communication baud rate, integer, and fractional parts
• number of data bits
• number of stop bits
• parity mode
• FIFO enable (16 deep) or disable (1 deep)
• FIFO trigger levels selectable between 1/8, 1/4, 1/2, 3/4, and 7/8.
• internal nominal 1.8432MHz clock frequency (1.42–2.12MHz) to generate
low-power mode shorter bit duration
• hardware flow control.
Additional test registers and modes are implemented for integration testing.
16.2.3 Interrupts
The interrupts signals from each UART are combined into a single interrupt that is
output to the VIC:
UART0 VIC interrupt line 12
UART1 VIC interrupt line 13
UART2 VIC interrupt line 14.
16.2.4 DMA
The DMA requests from each UART are combined into two DMA channels:
UART0 Tx DMA channel 15
UART0 Rx DMA channel 14
UART1 Tx DMA channel 13
UART1 Rx DMA channel 12
UART2 Tx DMA channel 11
UART2 Rx DMA channel 10.