Specifications

UART Controller
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 16-5
16.2.1 Clock signals
The UARTs can be clocks from an internal reference or the external reference clock
UARTCLKEXT can be selected.
The frequency selected for UARTCLK must accommodate the required range of baud
rates:
F
UARTCLK
(min) >= 16 x baud_rate (max)
F
UARTCLK
(max) <= 16 x 65535 x baud_rate (min)
For example, for a range of baud rates from 110–460800 baud the UARTCLK
frequency must be within the range 7.3728–115MHz.
The frequency of UARTCLK must also be within the required error limits for all baud
rates to be used.
There is also a constraint on the ratio of clock frequencies for PCLK to UARTCLK.
The frequency of UARTCLK must be no more than
5
/
3
times faster than the frequency
of PCLK:
F
UARTCLK
<=
5
/
3
x F
PCLK
This gives sufficient time to write the received data to the receive FIFO.
16.2.2 Registers
There are three PrimeCell UARTs in the ARM926EJ-S Development Chip. The base
addresses are:
UART0
0x101F1000 .
UART1
0x101F2000 .
UART3
0x101F3000.
The following locations are reserved, and must not be used during normal operation:
• locations at offsets
0x008 – 0x014 , and 0x01C are reserved and must not be accessed
• locations at offsets
0x04C – 0x07C are reserved for possible future extensions
• locations at offsets
0x080 – 0x08C are reserved for test purposes
• locations at offsets
0x90 – 0xFCC are reserved for future test purposes
• location used at offsets
0xFD0 – 0xFDC are used for future identification registers
• location used at offsets
0xFE0 – 0xFFC are used for identification registers.