Specifications
UART Controller
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 16-3
• Independent masking of transmit FIFO, receive FIFO, receive timeout, modem
status, and error condition interrupts.
Note
The interrupts signals from each UART are combined into a single interrupt that
is output to the VIC.
• Support for Direct Memory Access (DMA).
• False start bit detection.
• Line break generation and detection.
• Support of the modem control functions CTS, DCD, DSR, RTS, DTR, and RI.
• Programmable hardware flow control.
• Fully-programmable serial interface characteristics:
— data can be 5, 6, 7, or 8 bits
— even, odd, stick, or no-parity bit generation and detection
— 1 or 2 stop bit generation
— baud rate generation, dc up to UARTCLK_max_freq/16
• IrDA SIR ENDEC block providing:
— programmable use of IrDA SIR or PrimeCell UART input/output
— support of IrDA SIR ENDEC functions for data rates up to
115.2Kbits/second half-duplex
— support of normal 3/16 and low-power (1.41–2.23μs) bit durations
— programmable internal clock generator enabling division of reference clock
by 1–256 for low-power mode bit duration.
• Identification registers that uniquely identify the PrimeCell UART. These can be
used by an operating system to automatically configure itself.