Specifications

Dual Timer/Counters
15-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
Figure 15-1 shows a simplified block diagram of the module. At reset, the timers are
clocked by an external reference on the REFCLK32K input. You can use the system
controller to change the timer reference to the TIMCLKEXT input signal (see Clock
control on page 2-13).
Note
In Figure 15-1, test logic is not shown for clarity.
Figure 15-1 Simplified block diagram
15.2.1 Interrupts
The interrupt signals from the two counters are combined and output to VIC interrupt
line 10.
Core APB
AMBA APB
Interface
Load Register
Value Register
Background load Register
Control Register
Raw Interrupt Status Register
Masked Interrupt Status Register
Interrupt Clear Register
32/16-bit down counterPrescaler
Timer 1 Free Running Counter
timer clock
TIMCLKEN1
TIMCLKEN2
Load Register
Value Register
Background load Register
Control Register
Raw Interrupt Status Register
Masked Interrupt Status Register
Interrupt Clear Register
32/16-bit down counterPrescaler
Timer 2 Free Running Counter
TIMERINT1
TIMERINT2
TIMERINTC
Clock control
logic
(to VIC)
(Not used)
(Not used)
HCLK