Specifications

Synchronous Serial Port (SSP)
14-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
14.3 SSP signals on pads
The signals connected to pads are listed in Table 14-1.
Table 14-1 Pad signal descriptions
Name Type Description
SSPFSSOUT Output PrimeCell SSP frame, or slave select output (master).
SSPCLKOUT Output PrimeCell SSP clock output (master).
SSPRXD Input PrimeCell SSP receive data input.
SSPTXD Output PrimeCell SSP transmit data output.
nSSPCTLOE Output Output enable signal (active LOW) for SSPCLKOUT output from the
PrimeCell SSP. This output is cleared when the device is in master mode and
set when the device is in slave mode.
SSPFSSIN Input PrimeCell SSP frame input (slave).
SSPCLKIN Input PrimeCell SSP clock input (slave).
nSSPOE Output Output enable signal (active LOW) to indicate when SSPTXD is valid.
SSPCLKEXT Input External clock reference for peripheral. This signal can be selected instead of
the internal clock reference.