Specifications

Synchronous Serial Port (SSP)

14.2.2 Registers

The base address of the PrimeCell SSP is

0x101F4000

The following locations are reserved, and must not be used during normal operation:

• locations at offsets

0x028

–

0x07C

and

0xFD0

–

0xFDC

are reserved for possible future

extensions

• locations at offsets

0x080

–

0x088

are reserved for test purposes.

14.2.3 Interrupts

There are five interrupts generated by the PrimeCell SSP. Four of these are individual,

maskable, active HIGH interrupts:

SSPRXINTR PrimeCell SSP receive FIFO service interrupt request.

SSPTXINTR PrimeCell SSP transmit FIFO service interrupt request.

SSPRORINTR PrimeCell SSP receive overrun interrupt request.

SSPRTINTR PrimeCell SSP time out interrupt request.

The fifth is a combined single interrupt SSPINTR.

Note

Only the combined interrupt is connected to the interrupt controller. VIC interrupt line

11 is used for the SSP interrupt.

The status of the individual interrupt sources can be read from SSPRIS and SSPMIS

registers.

14.2.4 DMA

SSP transmit requests use DMA channel 9. SSP receive requests use DMA channel 8.