Specifications

Synchronous Serial Port (SSP)
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 14-3
• Programmable choice of interface operation, SPI, Microwire, or TI synchronous
serial.
• Programmable data frame size from 4 to 16 bits.
• Independent masking of transmit FIFO, receive FIFO, and receive overrun
interrupts.
• Internal loopback test mode available.
• Support for Direct Memory Access (DMA).
• Identification registers that uniquely identify the PrimeCell SSP. These can be
used by an operating system to automatically configure itself.
Figure 14-1 shows a block diagram of the PrimeCell SSP and the pad interface.
Figure 14-1 PrimeCell SSP block diagram
Tx and
Rx
FIFOs
APB
interface
Clock
control
SSPCLKEXT
Transmit/
receive
logic
DMA and
interrupt
SSPCLK
ARM926EJ-S Dev. Chip
Clock and
reset
controller
SSPRXD
SSPFSSIN
SSPCLKIN
nSSPCTLOE
SSPCLKOUT
SSPFSSOUT
SSPTXD
nSSPOE
PL022 SSP
DMA
APB
bus
Bus
matrix
AHB to
APB
bridge