Specifications

Synchronous Serial Port (SSP)

14.1 About the ARM PrimeCell SSP (PL022)

The PrimeCell Synchronous Serial Port (SSP) is an Advanced Microcontroller Bus

Architecture (AMBA) slave block that connects to the DMA APB. The PrimeCell SSP

is an AMBA compliant System-on-Chip (SoC) peripheral that is developed, tested, and

licensed by ARM.

The release version used is PL022 SSP REL1v2. The base address for the SSP control

registers is

0x101F4000

. For more information on the controller, see the ARM PrimeCell

Synchronous Serial Port Controller (PL022) Technical Reference Manual.

The PrimeCell SSP is a master or slave interface that enables synchronous serial

communication with slave or master peripherals having one of the following:

• a Motorola SPI-compatible interface

• a Texas Instruments synchronous serial interface

• a National Semiconductor Microwire interface.

In both master and slave configurations, the PrimeCell SSP performs:

• parallel-to-serial conversion on data written to an internal 16-bit wide, 8-location

deep transmit FIFO

• serial-to-parallel conversion on received data, buffering it in a similar 16-bit wide,

8-location deep receive FIFO.

Interrupts are generated to:

• request servicing of the transmit and receive FIFO

• inform the system that a receive FIFO over-run has occurred

• inform the system that data is present in the receive FIFO after an idle period has

expired.

14.1.1 Features of the PrimeCell SSP

The PrimeCell SSP has the following features:

• Compliance to the AMBA Specification (Rev 2.0) for easy integration into SoC

implementation.

• Master or slave operation.

• Programmable clock bit rate and prescale.

• Separate transmit and receive first-in, first-out memory buffers, 16 bits wide, 8

locations deep.