Specifications

Synchronous Static Memory Controller (SSMC)

nSMCS6 Output Chip select for bank 6 of external memory, default active LOW.

nSMCS7 Output Chip select for bank 7 of external memory, default active LOW.

nSMDATAEN[3:0] Output Tristate input/output pad enable for the byte lanes of the external

memory data bus SMDATA[31:0], active LOW. Enables the

byte lanes [31:24], [23:16], [15:8], and [7:0] of the data bus

independently.

nSMOEN Output Output enable for external memory banks, active LOW.

nSMWEN Output Write enable for the external memory banks, active LOW.

SMADDR[25:0] Output External memory address bus, to external memory banks.

SMADDRVALID Output External address valid output, used to indicate when the address

output is stable during synchronous burst transfers.

SMBAA Output External burst address advance signal. Used to advance the

address count in the external memory device.

nSMBLS[3:0] Output Byte lane select signals, active LOW. The signals

nSMBLS[3:0] select byte lanes [31:24], [23:16], [15:8], and

[7:0] on the data bus.

SMCLK[3:0] Output The clocks output to synchronous memory devices.

Table 13-2 Pad signals (continued)

Signal name Direction Description