Specifications

Synchronous Static Memory Controller (SSMC)

13.3 SSMC signals on pads

Table 13-2 describes the signals to the input/output pads.

Table 13-2 Pad signals

Signal name Direction Description

nSMBURSTWAIT[0] Input Synchronous burst wait input used by the external device to

delay a synchronous burst transfer.

SMBLS7POL Input This is used to define the reset value of bit 6 in SMBCR7

(nSMBLS):

0 = nSMBLS is active low (default)

1 = nSMBLS is active high.

SMCANCELWAIT Input This signal enables the system to recover from an externally

waited transfer that takes longer than expected to finish. Active

HIGH.

SMDATAIN[31:0] Input External input data bus used to read data from memory bank.

SMDATAOUT[31:0] Input External output data used to write data from SSMC to memory

bank.

SMFBCLK Input The feedback clock from the memory devices.

SMMWCS7[1:0] Input These static configuration bits indicate the memory width used

for boot memory bank one:

00 = 8-bit

01 = 16-bit

10 = 32-bit

11 = reserved.

SMWAIT Input Wait mode input from external memory controller. Active

HIGH or active LOW (default), as programmed in the SSMC

control registers for each bank.

nSMCS0 Output Chip select for bank 0 of external memory, default active LOW.

nSMCS1 Output Chip select for bank 1of external memory, default active LOW.

nSMCS2 Output Chip select for bank 2 of external memory, default active LOW.

nSMCS3 Output Chip select for bank 3 of external memory, default active LOW.

nSMCS4 Output Chip select for bank 4 of external memory, default active LOW.

nSMCS5 Output Chip select for bank 5 of external memory, default active LOW.