Specifications

Synchronous Static Memory Controller (SSMC)
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 13-5
13.2 Functional description
The SSMC core performs read and write accesses to external memory through the
AMBA AHB slave interface. Figure 13-1 shows a block diagram of the SSMC core.
Figure 13-2 on page 13-6 and Figure 13-3 on page 13-7 shows the data and control
signal multiplexing.
Figure 13-1 SSMC interface block diagram
GX175
MPMC
SMFBCLKIN SMFBCLK
nSMOEN
nSMWEN
SMADDR[25:0]
MPMC/SSMC multiplexor
SMDATA[31:0]
PL093
SSMC
Clock and reset
controller
ARM926EJ-S
Dev. Chip
Configuration
CFGMPMCnSMC
nSMBLS[3:0]
HCLK
SMCLK[2:0]
SMBAA
SMADDRVALID
SMWAIT
SMCANCELWAIT
SMBURSTWAIT
SMCLK[2:0]
SMBAA
SMADDRVALID
SMWAIT
SMCANCELWAIT
SMBURSTWAIT
SMADDR[25:0]
nSMBLS[3:0]
nSMOEN
nSMWEN
nSMCS[6:4] nSTATICCS[6:4]
nSMCS1 nSTATICCS7
nSTATICCS0nSMCS0
nSMCS7
nSMCS2
nSMCS3
nSTATICCS1
nSTATICCS2
nSTATICCS3
SMDATAIN[31:0]
SMDATAOUT[31:0]
nSMDATAEN[3:0]
SMBBLS7POL
SMBIGENDIAN
SMMEMCLKDELAY
SMMEMCLK
SMMEMCLKRATIO[1:0]
SMFBCLK[3:0]