Specifications

Synchronous Static Memory Controller (SSMC)

• external asynchronous wait control

• configurable size at reset for boot memory bank using external control pins

• system testing using externally applied TIC vectors through built-in TIC AMBA

master block

• support to interface to another memory controller using an External Bus Interface

(EBI)

• multiple memory clock frequencies available, HCLK, HCLK/2, and HCLK/3

• eight word, 32-bit, wrapping reads from 16-bit or 32-bit memory.

13.1.2 Programmable parameters

The following key parameters are programmable for each memory bank:

• external memory width, 8, 16, or 32-bit

• burst mode operation

• write protection

• external wait control enable

• external wait polarity

• write WAIT states for static RAM devices

• read WAIT states for static RAM and ROM devices

• initial burst read WAIT state for burst devices

• subsequent burst read WAIT state for burst devices

• read byte lane enable control

• bus turn-around (idle) cycles

• output enable and write enable output delays.