Specifications

Synchronous Static Memory Controller (SSMC)

13.1 About the ARM PrimeCell SSMC (PL093)

The PrimeCell Synchronous Static Memory Controller (SSMC) is an Advanced

Microcontroller Bus Architecture (AMBA) compliant System-on-Chip peripheral that

is developed, tested, and licensed by ARM. The SSMC connects to the AHB bus matrix.

The release version used is PL093 SSMC r0p0-00ltd0. The base address for the SSMC

control registers is

0x10100000

. For more information on the controller, see the ARM

PrimeCell Static Memory Controller (PL093) Technical Reference Manual. For further

information on AMBA refer to the AMBA Specification.

13.1.1 Features of the PrimeCell SSMC

The PrimeCell SSMC macro block offers the following features:

• soft macrocell available in both VHDL and Verilog

• fully scan insertable design

• functional verification using ARM BusTalk functional test environment

• compatibility with AMBA AHB on-chip bus systems.

The PrimeCell SSMC supports:

• asynchronous static memory-mapped devices including RAM, ROM, and flash

• synchronous static memory-mapped devices including synchronous burst flash

• asynchronous page mode read operation in nonclocked memory subsystems

• asynchronous burst mode read access to burst mode ROM and flash devices

• 8, 16, and 32-bit wide external memory data paths

• little-endian and big-endian memory architectures

• AHB burst transfers

• independent configuration for up to eight memory banks, each up to 64MB

• programmable wait states (up to 31)

• programmable bus turnaround cycles (up to 15)

• programmable output enable and write enable delays (up to 15)

• write enable and byte lane select outputs for use with 32, 16, or 8-bit SRAM

devices

• independent byte lane control for each memory bank