Specifications

Smart Card Interface (SCI)
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 12-5
12.2.3 Interrupts
There are fifteen interrupts generated within the PrimeCell SCI. The interrupt mask set
or clear register, SCIIMSC, provides a way of masking each of these individual
interrupts. Setting the appropriate mask bit HIGH enables the interrupt, all of these are
active HIGH.
Individual interrupts are shown in Table 12-1.
A single interrupt, SCIINTR, that is the combinatorial OR of the fifteen individual
interrupts is output to the VIC interrupt line 15.
Table 12-1 Interrupts
Name Description
SCICARDININTR SCI Card In interrupt
SCICARDOUTINTR SCI Card Out interrupt
SCICARDUPINTR SCI Card powered Up interrupt
SCICARDDNINTR SCI Card powered Down interrupt
SCITXERRINTR SCI Transmit Error interrupt
SCIATRSTOUTINTR SCI Answer-To-Reset Start Time Out interrupt
SCIATRDTOUTINTR SCI Answer-To-Reset data stream Duration Time
Out
SCIBLKTOUTINTR SCI Block Time Out interrupt
SCICHTOUTINTR SCI Character Time Out interrupt
SCIRTOUTINTR SCI Read Time Out interrupt
SCIRORINTR SCI Overrun interrupt
SCICLKSTPINTR SCI Clock Stopped interrupt
SCICLKACTINTR SCI Clock Active interrupt
SCIRXTIDEINTR SCI Receive FIFO Tide level interrupt
SCITXTIDEINTR SCI Transmit FIFO Tide level interrupt.