Specifications

Smart Card Interface (SCI)
12-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
12.2 Functional description
The block diagram of the SCI is shown in Figure 12-1.
Figure 12-1 SCI block diagram
12.2.1 Registers
The base address of the PrimeCell SCI is
0x101F0000 .
The following locations are reserved, and must not be used during normal operation:
• locations at offset
0x101F0088 – 0x101F0EFC are reserved and must not be used
• locations at offsets
0x101F0F00 – 0x101F0F10 are reserved for test purposes
• locations at offsets
0x101F0F14 – 0x101F0FCC are reserved and must not be used
• locations at offsets
0x101F0FD0 – 0x101F0FDC are reserved for possible future
extensions.
12.2.2 DMA
SCI Tx DMA requests go to DMA channel 7. SCI Rx requests go to channel 6.
SCICLKININ
SCIDETECTIN
SCIDATAININ
SCICLKIN
SCIDETECT
SCIDATAIN
SCIREFCLKEXT
PL131 SCI
Clock and reset
controller
ARM926EJ-S
Dev. Chip
SCIREFCLKEXTIN
nSCIDATAOUTEN
SCIDATAOUTOD
SCICLKOUTSCICLKOUTOUT
nSCICLKENnSCICLKENOUT
nSCIDATAEN
nSCIDATAENOUT
nSCICARDRST
SCIVCCEN
SCIFCB
nSCICARDRSTOUT
SCIVCCENOUT
SCIFCBOUT
nSCICLKOUTEN
nSCIDATAOUTEN
LOW
SCIDEACREQ
NC
SCIDEACACK
LOW
SCICLK
Interrupt
and DMA
DMA
APB
bus
Bus
matrix
AHB to
APB
bridge