Specifications

Real-Time Clock (RTC)

11.2.1 Registers

The base address of the PrimeCell RTC is

0x101E8000

The following locations are reserved, and must not be used during normal operation:

• locations at offsets

0x20

–

0x7C

and

0x94

–

0xFCC

are reserved for possible future

extensions

• locations at offsets

0x80

–

0x90

are reserved for test purposes

• locations at offsets

0xFD0

–

0xFDC

are reserved for future identification registers.

11.2.2 Interrupts

A single, maskable, active HIGH interrupt RTCINTR is generated by the PrimeCell

RTC when a match occurs between the counter and the equivalent match value:

• This interrupt is enabled or disabled by changing the mask bit in RTCIMSC. To

enable the interrupt, set bit 0 HIGH.

• The status of the interrupt mask can be read from bit 0 of RTCMIS.

• Writing 1 to bit 0 of RTCICR clears the RTCINTR flag.

• The RTC interrupt, RTCINTR, is output to the interrupt controller.

• The RTC interrupt drives interrupt line 10 of the VIC.