Specifications

Multi-Port Memory Controller (MPMC)
10-8 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
10.3 MPMC signals on pads
The pad interface and control signals are described in Table 10-1.
Table 10-1 Pad interface and control signal descriptions
Name Type
Source/
destination
Description
MPMCADDROUT[25:15] Output MPMC/SSMC
multiplexor
Address output. Used for static memory devices.
Note
SDRAM memories only use MPMCADDROUT[14:0].
Static memories use bits MPMCADDROUT[25:0].
MPMCADDROUT[14:0] Output Pad and
MPMC/SSMC
multiplexor
Address output. Used for both static and SDRAM devices.
MPMCCKEOUT[3:0] Output Pad SDRAM clock enables. Used for SDRAM devices.
MPMCCLKOUT[3:0] Output Pad SDRAM clock out. Used for SDRAM devices.
MPMCDATAIN[31:0] Input Pad and
MPMC/SSMC
multiplexor
Read data from memory. Used for the static memory
controller, the dynamic memory controller and the TIC.
MPMCDATAOUT[31:0] Output Pad and
MPMC/SSMC
multiplexor
Data output to memory. Used for the static memory
controller, the dynamic memory controller and the TIC.
MPMCDATAOUTEN[3:0] Output Pad and
MPMC/SSMC
multiplexor
Enable data out onto external memory bus byte lanes.
MPMCDQMOUT[3:0] Output Pad Data mask output to SDRAMs. Used for SDRAM devices.
MPMCFBCLKIN[3:0] Input Pad SDRAM feedback clock in. Used for SDRAM devices.
MPMCRPVHHOUT Output Pad Voltage control for Micro Syncflash reset signal (RP).
nMPMCBLSOUT[3:0] Output MPMC/SSMC
multiplexor
Byte lane select, active LOW, for static memories. Used
for static memory devices.
nMPMCCASOUT Output Pad Column address strobe. Used for SDRAM devices.
nMPMCDYCSOUT[3:0] Output Pad SDRAM chip selects. Used for SDRAM devices.
nMPMCOEOUT Output MPMC/SSMC
multiplexor
Output enable for static memories. Used for static memory
devices.