Specifications

Multi-Port Memory Controller (MPMC)
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 10-7
10.2.1 Implementation details
The following outputs are unconnected:
• MPMCDLLCALIBREQ
• MPMCDQSOUT[1:0]
• nMPMCCLKOUT[3:0]
• nMPMCDQSOUTEN[3:0]
• MPMCEBIREQ.
Note
Booting from memory controlled by the MPMC is not supported. Configuration signals
relating to configuring the reset state of the MPMC are not used. You must configure
the MPMC before you use it to control memory on either the dynamic or static memory
buses.
The MPMCx signals from the configuration block (shown in MPMC PrimeCell block
diagram on page 10-6) are reserved for future use and are not supported in this release
of the ARM926EJ-S Development Chip.