Specifications

Multi-Port Memory Controller (MPMC)
10-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
10.2 Functional description
Figure 10-1 shows a block diagram of the PrimeCell MPMC. For details on the static
memory multiplexor, see Functional description on page 13-5.
Figure 10-1 MPMC PrimeCell block diagram
MPMCTESTIN
nMPMCADDROUT[14:0]
MPMCCLKOUT[3:0]
MPMCTEST
MPMCFBCLKIN MPMCFBCLK
MPMCCLK[4:0]
MPMCCLKEOUT[3:0] MPMCCLKE[3:0]
MPMCDQMOUT[3:0] MPMCDQM[3:0]
MPMCDYCSOUT[3:0] MPMCDYCS[3:0]
nMPMCRASOUT MPMCRAS
nMPMCCASOUT MPMCCAS
MPMCRPOUTOUT MPMCRPOUT
MPMCRPVHHOUTOUT MPMCRPVHHOUT
MPMCDATAOUT[31:0]
nMPMCADDR[14:0]
nSMOEN
nMPMCWEOUT nMPMCWE
nSMWEN
SMADDR[25:0]
nMPMCADDROUT[27:15]
MPMC/SSMC multiplexor
MPMCDATAIN[31:0]
MPMCDATAOUTEN0[3:0]
MPMCDATA[31:0]
SMDATA[31:0]
PL093 SSMC
Clock and
reset
controller
ARM926EJ-S Dev. Chip
Configuration
CFGMPMCnSMC
GX175
MPMC
Register
interface
AHB
interface
MPMCOEOUT
nMPMCBLSOUT[3:0]
nSMBLS[3:0]
nMPMCSTCSOUT[3:0]
nSTATICCS[3:0]
MPMCBIGENDIAN
MPMCSTCSxPOL
MPMCCLKDELAY
MPMCREL1CONFIG
MPMCSTCS1PB
MPMCSTCS1MW[1:0]
MBX
interface
AHB
interface
AHB
interface
AHB
interface
Bus matrix
MPX
Refresh
HCLKx
MPMCFBCLKIN[3:0]