Specifications

Multi-Port Memory Controller (MPMC)

• Power-saving modes dynamically control MPMCCKEOUT and

MPMCCLKOUT.

• Dynamic memory self-refresh mode supported by a Power Management Unit

(PMU) interface or by software.

• Controller supports 2K, 4K, and 8K row address synchronous memory parts. That

is, typical 512Mb, 256Mb, 128Mb, and 16Mb parts, with 8, 16, or 32 DQ (data)

bits per device.

• Two reset domains enable dynamic memory contents to be preserved over a soft

reset.

• A separate AHB interface for programming the MPMC registers. Enables the

MPMC registers to be situated in memory with other system peripheral registers.

• Locked AHB transactions supported.

• Support for all AHB burst types.

• Little and big-endian support.

• Support for the External Bus Interface (EBI) that enables the memory controller

pads to be shared.

• PrimeCell ID support.

Note

Synchronous static memory devices (burst mode devices) are not supported and DDR

SDRAM devices are not supported.