Specifications

Multi-Port Memory Controller (MPMC)

10.1 About the ARM PrimeCell MPMC (GX175)

The PrimeCell MPMC is an Advanced Microcontroller Bus Architecture (AMBA)

compliant System-on-Chip (SoC) peripheral that is developed, tested, and licensed by

ARM Limited. It connects to the AHB bus matrix.

The release version used for the controller is GX175 MPMC r0p0-00alp2. The base

address for the MPMC control registers is

0x10110000

. For more information on the

memory controller, see the ARM PrimeCell Multiport Memory Controller (GL175)

Technical Reference Manual.

10.1.1 Features of the PrimeCell MPMC

The PrimeCell MPMC offers:

• AMBA 32-bit AHB compliancy.

• Dedicated MBX Interface Port for direct connection to the ARM range of MBX

3D Graphics Cores.

• Dynamic memory interface supports SDRAM and low-power variants.

• Asynchronous static memory device support including RAM, ROM, and Flash,

with or without asynchronous page mode.

• Specifically designed for cached processors.

• Designed to work with noncritical word first, and critical word first processors,

such as the ARM926EJ-S.

• Read and write buffers to reduce latency and to improve performance.

• Five AHB interfaces for accessing external memory.

• 8-bit, 16-bit, and 32-bit wide static memory support.

• 16-bit and 32-bit wide databus SDRAM.

• Static memory features include:

— asynchronous page mode read

— programmable wait states

— bus turnaround cycles

— output enable, and write enable delays

— extended wait.

• Four chip selects for synchronous memory and four chip selects for static memory

devices.