Specifications
General Purpose Input Output (GPIO)
9-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
Note
For GPIO3, the GPAFIN[6:0] signals are not used, but the GPAFIN[7] signal is
connected to the system controller BATOK signal.
For GPIO0, GPIO1, and GPIO2, none of the GPAFIN[7:0] signals are not used
9.2.1 Registers
The base address of the PrimeCell GPIO’s are:
GPIO0
0x101E4000
GPIO1
0x101E5000
GPIO2
0x101E6000
GPIO2
0x101E7000
.
Some locations within the memory range are reserved:
•offsets
0x424
–
0xFCC
are reserved for possible future extensions and test purposes
•offsets
0xFDO
–
0xFDC
are reserved for future ID expansion.
9.2.2 Implementation details
Table 9-1 describes the tied-off or unused signals. Replace x with 0–3 for
GPIO0–GPIO3.
Table 9-1 On-chip signal descriptions
Name
Source/
destination
Description
nGPAFENx[7:0] HIGH Hardware control output enable, active LOW. If not utilized
these pins must be tied HIGH.
GPAFOUTx[7:0] HIGH Hardware control data input. If not utilized these pins can be
tied LOW or HIGH.
GPAFINx[7:0] Not used
Hardware control data output.
Note
For GPIO3, the GPAFIN[7] signal is output to the BATOK
signal in the system controller.