Specifications

General Purpose Input Output (GPIO)

9.1 About the ARM PrimeCell GPIO (PL061)

The PrimeCell GPIO is an Advanced Microcontroller Bus Architecture (AMBA)

compliant System-on-Chip (SoC) peripheral that is developed, tested, and licensed by

ARM. The four GPIOs connect to the core APB.

The release version used is PL061 GPIO 1v0. The base address for the GPIO registers

are

0x101E4000

0x101E5000

0x101E6000

, and

0x101E7000

. For more information on the

controller, see the ARM PrimeCell GPIO (PL061) Technical Reference Manual.

The PrimeCell GPIO provides eight programmable general purpose inputs or outputs

that you can control through an APB bus interface.

Four GPIO PrimeCells are instantiated to give a 32-bit wide port. An interrupt interface

is provided to configure any number of pins as interrupt sources. You can generate

interrupts depending on a level, or a transitional value of a pin. At system reset,

PrimeCell GPIO lines default to inputs. The PrimeCell GPIO interfaces with input and

output pad cells using a data input, data output, and output enable per pad.

9.1.1 Features of the PrimeCell GPIO

The PrimeCell GPIO offers:

• Compliance to the AMBA Specification (Rev 2.0) onwards for easy integration

into SoC implementation.

• Individually programmable input/output pins, default to input at reset.

• Programmable interrupt generation capability, from a transition or a level

condition, on any number of pins.

Note

Each of the four GPIO blocks has a connection to the VIC.

• Bit masking in both read and write operations through address lines.

• Identification registers that uniquely identify the PrimeCell GPIO.