Specifications

Direct Memory Access Controller (DMAC)

8.2.1 Peripheral integration

The allocation of the DMAC peripheral request lines is defined in Table 8-1.

The master interfaces of the DMAC both drive single master AHBs. Therefore:

• the HGRANT inputs are tied HIGH

• the HBUSREQ outputs are left unconnected.

The only interrupt from the DMAC that is connected to the VIC is the combined

interrupt source DMACINTR. The remaining interrupt sources, DMAINTERR and

DMAITTC, are left unconnected.

Table 8-1 DMA channel allocation

DMA requester DMA channel

UART0 Tx 15

UART0 Rx 14

UART1 Tx 13

UART1 Rx 12

UART2 Tx 11

UART2 Rx 10

SSP Tx 9

SSP Rx 8

SCI Tx 7

SCI Rx 6

External DMA request [5:0] 5:0