Specifications

Direct Memory Access Controller (DMAC)

• Programmable DMA burst size. The DMA burst size can be programmed to more

efficiently transfer data. Usually the burst size is set to half the size of the FIFO

in the peripheral.

• Internal four-word FIFO per channel.

• Supports 8, 16, and 32-bit wide transactions.

• Big-endian and little-endian support. The PrimeCell DMAC defaults to

little-endian mode on reset.

• Separate and combined DMA error and DMA count interrupt requests. An

interrupt to the processor can be generated on a DMA error or when a DMA count

has reached 0 (this is usually used to indicate that a transfer has finished). The

following interrupt request signals are used to do this:

— DMACINTTC is used to signal when a transfer has completed.

— DMACINTERR is used to signal when an error has occurred.

— DMACINTR combines both the DMACINTTC and DMACINTERR

interrupt request signals. The DMACINTR interrupt request can be used in

systems that have few interrupt controller request inputs.

• Interrupt masking. The DMA error and DMA terminal count interrupt requests

can be masked.

• Raw interrupt status. The DMA error and DMA count raw interrupt status can be

read prior to masking.

• Identification registers that uniquely identify the PrimeCell DMAC. These can be

used by an operating system to automatically configure itself.

Note

The DMA system cannot access the TCM memory located in the ARM926EJ-S

Development Chip.