Specifications

Direct Memory Access Controller (DMAC)

8.1 About the Direct Memory Access Controller (PL080)

The DMAC is an Advanced Microcontroller Bus Architecture (AMBA) compliant

System-on-Chip (SoC) peripheral that is developed, tested, and licensed by ARM

Limited.

The DMAC is an AMBA AHB module, and has two masters and one slave that connect

to the AHB bus matrix.

The release version used is PL080 DMAC REL1v1. The base address for the DMAC

registers is

0x10130000

. For more information on the controller, see the ARM PrimeCell

DMA (PL080) Technical Reference Manual.

8.1.1 Features of the PrimeCell DMAC

The PrimeCell DMAC offers:

• Compliance to the AMBA Specification for easy integration into SoC

implementation.

• Eight DMA channels. Each channel can support a unidirectional transfer.

• 16 DMA requests. The PrimeCell DMAC provides 16 peripheral DMA request

lines.

• Single DMA and burst DMA request signals. Each peripheral connected to the

PrimeCell DMAC can assert either a burst DMA request or a single DMA request.

The DMA burst size is set by programming the PrimeCell DMAC.

• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

peripheral-to-peripheral transfers.

• Scatter or gather DMA is supported through the use of linked lists.

• Hardware DMA channel priority. Each DMA channel has a specific hardware

priority. DMA channel 0 has the highest priority down to channel 7 that has the

lowest priority. If requests from two channels become active at the same time the

channel with the highest priority is serviced first.

• AHB slave DMA programming interface. The PrimeCell DMAC is programmed

by writing to the DMA control registers over the AHB slave interface.

• Two AHB bus masters for transferring data. These interfaces are used to transfer

data when a DMA request goes active.

• 32-bit AHB master bus width.

• Incrementing or non-incrementing addressing for source and destination.