Specifications

MBX HR-S Graphics Accelerator
7-8 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
Figure 7-2 MMU address translation
Bits [31:12] Bits [11:0]
Page start address
Reserved (zero)
Translation table page 0 start address
register
Bits [31:12] Bits [11:0]
Page start address
Reserved (zero)
Translation table page 1 start address
register
Bits [31:12] Bits [11:0]
Page start address
Reserved (zero)
Translation table page 2 start address
register
Bits [31:12] Bits [11:0]
Page start address
Reserved (zero)
Translation table page 3 start address
register
Bits [31:12] Bits [11:0]
Page start address
Reserved (zero)
Translation table page 4 start address
register
Bits [31:12] Bits [11:0]
Page start address
Reserved (zero)
Translation table page 5 start address
register
Bits [31:12] Bits [11:0]
Page start address
Reserved (zero)
Translation table page 6 start address
register
Bits [31:12] Bits [11:0]
Page start address
Reserved (zero)
Translation table page 7 start address
register
Bits [22:10] Bits [9:0]
Linear local word address. 32MB range
Translation table in
fragmented system memory
Bits [31:12] Bits [11:0]
Translated page start
address
Reserved
Page 0 - 1K words
Page 1
Page 3
Page 4
Page 5
Page 6
Page 7
Bits [29:10] Bits [9:0]
Fragmented system word address. 4GB range.
Static registers