Specifications

MBX HR-S Graphics Accelerator

7.2.3 GX port memory interface

The MBX HR-S contains an MMU that maps the 8192 4KB pages making up the 32MB

linear address space of the MBX into 4KB (potentially) fragmented pages in the 4GB

system memory space.

Translation is performed using a table with 8KB entries, one for each 4KB page in a

32MB linear address space. Each entry is a word, so 32KB must be allocated for the

translation table. Table entries are byte-aligned.

The translation table resides in the 4GB fragmented address space. Eight static registers

are provided that point to eight 4KB pages containing the table. A 256-entry, four-way

set associative cache of the translation table is maintained within the MBX HR-S core.

The MMU is bypassed on reset. The 32MB linear address space is mapped directly into

the bottom of the 4GB address space. When enabled, approximately 256 cycles are

required to initialize the cache. A flag, made available in the MMU enable register, is

set when the cache is ready. If the cache is subsequently disabled, the MMU returns to

the bypass state.

To update the translation table the MMU must first be disabled. The table can then be

changed and the MMU re-enabled. This procedure is required to invalidate all table

entries in the cache.

Figure 7-2 on page 7-8 shows the MMU address translation.