Specifications

MBX HR-S Graphics Accelerator
7-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
7.2 Memory map and registers
The MBX HR-S memory map is described in the following sections:
• MBX HR-S registers
• AHB slave interface
• GX port memory interface on page 7-7.
7.2.1 MBX HR-S registers
The MBX control registers are located starting at memory location
0x140000000 .
For detailed information on the MBX registers, see the ARM MBX HR-S Graphics Core
Technical Reference Manual.
7.2.2 AHB slave interface
The ARM MBX HR-S can be placed anywhere within a SoC memory map, and is
defined by the SoC architect. Its main SoC interface has an input address range of 16MB
that is arranged as shown in Table 7-1.
Table 7-1 MBX HR-S memory map
Description
Memory address
range
Registers
0x40000000 – 0x407FFFFF
TA d ata 0x40800000 – 0x409FFFFF
TA 2D data 0x40A00000 – 0x40BFFFFF
TA control 0x40C00000 – 0x40FFFFFF