Specifications

MBX HR-S Graphics Accelerator

7.1.2 Functional overview

PowerVR technology is implemented as a display list renderer. Groups of polygons are

batched together into a display list before being processed by the 3D rendering

hardware. This is fundamentally different to the approach used by conventional

systems, because it enables a scene to be partitioned into small tiles or regions, each of

which is rendered independently. This has the following benefits:

Performance

Because the region is only a small subset of the whole scene, the ARM

MBX HR-S can implement key operations on-chip without frequent

access to external memory. Hidden Surface Removal (HSR), or

Z-buffering, is done with an on-chip Z-buffer and display pixel

processing and blending also uses an on chip frame buffer tile as a local

storage. This means that the majority of external memory accesses

normally performed by a conventional 3D system are eliminated. All the

on-chip processing is performed at high depth and pixel accuracy at full

clock rate, without having to wait for Z-buffer or frame buffer memory

accesses that slow down conventional 3D systems.

Deferred texturing

In PowerVR systems, the HSR is completed in the first phase of the

pipeline before texturing and shading. Because of this, only visible pixels

to be finally drawn in the display memory are textured and shaded. This

eliminates both the redundant work performed and, most importantly, the

redundant texture fetches from memory required by conventional 3D

systems.

Accuracy and image quality

Z-buffering and pixel blending are done entirely on-chip, so they can be

performed at high precision with no performance degradation or increase

in memory bandwidth requirements. In PowerVR all pixel blend

operations are performed with true color precision, irrespective of the

number of translucent layers or the bit-depth of the frame buffer (Internal

True Color). This results in high image quality without performance loss