Specifications

MBX HR-S Graphics Accelerator
7-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
7.1 About the ARM MBX HR-S
The ARM MBX HR-S is an Advanced Microcontroller Bus Architecture (AMBA)
compliant System-on-a-Chip (SoC) component. Figure 7-1 shows a top-level block
diagram of the ARM MBX HR-S. The MBX component connects directly to the
MPMC and the AHB bus matrix.
Figure 7-1 ARM MBX HR-S top level block diagram
The ARM MBX consists of the following modules:
• Tile Accelerator (TA)
• event manager
• Vertex Geometry Processor (VGP)
• display list parser
• Hidden Surface Removal (HSR) engine
• texture shading unit
• texture cache
• pixel blender.
The release version used is r1p2. The base address for the MBX registers is
0x40000000 .
The modules are described in more detail in the ARM MBX HR-S Graphics Core
Technical Reference Manual.
SoC
interface
Event
manager
AHB
Tile
accelerator
VGP
HSR
engine
Texture
shading
unit
Pixel
blender
Texture
cache
Display list
parser
Arbiter
Memory interface
Display list
Z-buffer
read/write
Display list
Texture
Frame buffer write