Specifications

Color LCD Controller (CLCDC)

Cursor Masked Interrupt Status Register

The ClcdCrsrMIS Register is read-only. It is set to indicate a cursor interrupt providing

that the interrupt bit is not masked.

Figure 5-15 shows the register bit assignments.

Figure 5-15 ClcdCrsrMIS Register bit assignments

Table 5-10 lists the register bit assignments.

Undefined

31 10

CrsrMIS

Table 5-10 ClcdCrsrMIS Register bit assignments

Bit Name Function

[31:1] - Reserved, read undefined.

[0] CrsrMIS The cursor interrupt status is set immediately after the last data read from the cursor image

for the current frame, providing that the corresponding bit in the ClcdCrsrIMSC Register

is set.

The bit remains clear if the ClcdCrsrIMSC Register is clear.

This bit is cleared by writing to the ClcdCrsrICR Register. See Cursor Interrupt Clear