Specifications

Color LCD Controller (CLCDC)
ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 5-25
Cursor Raw Interrupt Status Register
The ClcdCrsrRIS Register is read-only. It is set to indicate a cursor interrupt, and, when
enabled, controls the state of the interrupt signal to the system interrupt controller.
Note
The ClcdCrsrRIS Register is valid regardless of the state of the CrsrIMSC bit.
Figure 5-14 shows the register bit assignments.
Figure 5-14 ClcdCrsrRIS Register bit assignments
Table 5-9 lists the register bit assignments.
Undefined
31 10
CrsrRIS
Table 5-9 ClcdCrsrRIS Register bit assignments
Bit Name Function
[31:1] - Reserved, read undefined.
[0] CrsrRIS The cursor interrupt status is set immediately after the last data read from the cursor
image for the current frame.
This bit is cleared by writing to the CrsrIC bit in the ClcdCrsrICR Register. See
Cursor Interrupt Clear Register on page 5-24.