Specifications

Color LCD Controller (CLCDC)

Operation

All cursor programming registers are accessed through the CLCDC slave interface. The

cursor image is held in the CLCDC in a 256x32-bit dual-port RAM.

When enabled, the hardware cursor uses the horizontal and vertical synchronization

signals, along with a pixel clock enable and various display parameters to calculate the

current scan coordinate such as:

• Horizontal Back Porch (HBP)

• Vertical Back Porch (VBP)

• Horizontal ACtive line (HAC)

• Vertical Active Column (VAC)

• Pixels-Per-Line (PPL)

• Lines-Per-Panel (LPP).

When the display point is inside the bounds of the cursor image, the cursor replaces

frame buffer pixels with cursor pixels.

The image RAM offers single cycle performance to enable the read to take place in the

clock cycle preceding its use, and maintains the data output until the next access. This

removes the requirement for a holding register.

When the last cursor pixel is displayed, an interrupt is generated that can be used by

software as an indication that it is safe to modify the cursor image. This enables

software controlled animations to be performed without flickering for frame

synchronized cursors.

Supported cursor sizes

Table 5-2 shows the two cursor sizes that are supported.

Table 5-2 Supported cursor images

X Pixels Y Pixels Bits per pixel Words per line Words in cursor image

32 32 2 2 64

64 64 2 4 256