Specifications
Color LCD Controller (CLCDC)
5-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B
5.2.1 Registers
The base address of the ARM PrimeCell CLCDC is
0x10120000
.
The following locations are reserved, and must not be used during normal operation:
• locations
0x10120050
–
0x101201FC
are reserved for possible future extensions
• locations
0x10120400
–
0x101207FF
are reserved for test purposes
• locations
0x10120C30
–
0x10120FDC
are reserved for possible future extensions.
The following locations have a different function in the ARM926EJ-S Development
Chip PL110 than that used is the standard PL110 controller:
• locations
0x10120018
–
0x1012001C
are swapped (see Table 5-1).
• locations
0x10120800
–
0x10120C2C
are used for the hardware cursor (see Hardware
cursor registers on page 5-17).
• locations
0x10120FE0
–
0x10120FFC
are the CLCD Peripheral ID and PrimeCell ID
registers.
Table 5-1 PrimeCell CLCDC register differences
Address
(Dev.
Chip)
Reset value
(Dev. Chip)
Description in PL110
TRM
Difference for CLCDC in ARM926EJ-S
Development Chip
0x10120018 0x0
LCDControl, LCD panel
pixel parameters
CLCDC TRM lists address as
0x1012001C
0x1012001C 0x0
LCDIMSC, interrupt mask
set and clear
CLCDC TRM lists address as
0x10120018
0x10120800–
0x10120C2C
0x0
Not present Hardware cursor registers from PL111 (see the
ARM926EJ-S Technical Reference Manual for details)
0x10120FE0 0x93
CLCDPeriphID0 CLCDC TRM lists value as
0x10
0x10120FE4 0x10
CLCDPeriphID1 CLCDC TRM lists value as
0x11