Specifications

Color LCD Controller (CLCDC)

Besides data formatting, the CLCDC provides a set of programmable display control

signals, that include:

• LCD panel power enable

• pixel clock

• horizontal and vertical synchronization pulses

• display bias.

The CLCDC uses the external clock source CLCDCLKEXT for timing the pixel clock.

The CLCDC data output can be converted to a VGA display signal by adding an

external Digital to Analog Converter (DAC).

• upper or lower panel DMA FIFO underflow

• base address update signification

• vertical compare

•bus error.

There is also a single combined interrupt that is raised when any of the individual

interrupts become active. The combined interrupt signal is output to interrupt 16 of the

VIC.

5.1.1 Hardware cursor support

The PL110 controller in the ARM926EJ-S Development Chip has been extended to

include a hardware cursor extension that reduces software overheads associated with

maintaining a cursor image in the CLCDC frame buffer (see Hardware cursor extension

to PL110 on page 5-7).